Integrated circuits, including application specific integrated circuits (ASICs), typically comprise a number of internal storage elements and latches. It is often desirable to clock these elements using different phases of a clock signal. For example, a master-slave latch typically requires two separate phases, one to clock the master latch and the other to clock the slave. A number of prior art schemes have been developed to generate multiple-phase clock signals. Unfortunately, prior art clock generation schemes suffer from a number of drawbacks.
One prior art phase generation scheme uses a clock distribution tree to distribute a single clock phase throughout the integrated circuit. To produce a second phase at selected storage elements, an inverter is inserted at the end of the clock tree. The normal clock signal provides one phase, while the output of the inverter provides a second phase. Such a scheme is disadvantageous, especially in CMOS integrated circuits. Because of the large process variations inherent in CMOS circuits, the delay through inverters at different locations within the circuit is likely to vary, producing a high degree of skew in the second phase.
Performance of an integrated circuit can be enhanced by minimizing skew between the various phases generated by a multiple-phase clock signal generator and by precisely controlling the placement of the clock edges of different phases. Some prior art phase generation schemes are disadvantageous, particularly in master-slave latch designs, because they do not provide precise edge placement and often introduce a measurable delay between the falling edge of the master latch clock phase and the rising edge of the slave latch clock phase.
A number of prior art phase generation schemes use a single 2.times. clock to generate two different clock signal phases. Unfortunately, these prior art schemes cannot produce more than two phases from the single high frequency clock. Many integrated circuits require four or more different phases of a clock signal to control the wide variety of storage elements in the circuit.
Given the disadvantages of many prior art phase generation schemes, there is a need for a multiple-phase clock signal generator for use in integrated circuit applications that achieves very precise edge placement and minimizes skew between the various phases. Additionally, such a multiple-phase clock signal generator should be suitable for use in CMOS integrated circuits despite the large process variations that occur throughout a CMOS circuit. Lastly, any such multiple-phase clock signal generator should be capable of producing two or more phases of a clock signal from a single high frequency clock. The present invention satisfies these needs.